Guide to the John L. Hennessy personal papers SC1362
Note
Subjects and Indexing Terms
Series 1. Publications Accession ARCH-2017-269
Computer Architecture a Quantitative Approach
Maryland
Flash Slides ARPA
DASH (1 of 2)
DASH (2 of 2)
EE182: Computer Architecture and Organization Information Sheet
Computer Architecture a Quantitative Approach
Tau Beta Pi Teaching Survey Winter Quarter
Tau Beta Pi Teaching Survey Spring Quarter
Tau Beta Pi Teaching Survey Autumn Quarter
Tau Beta Pi Engineering Course Evaluations Spring Quarter
Tau Beta Pi Engineering Course Evaluations Autumn Quarter
Tau Beta Pi Engineering Course Evaluations Winter Quarter
Endowed Professorships Directorships at Stanford University
Booklet of Abstracts and Viewgraphs Stanford Computer Forum
DEC System -10/20 Hardware Manual
CSL, Abstracts
A 160nS 54bit CMOS Division Implementation using Self-timing and symmetrically overlapped SRT stages
A 4 nsec 4Kxlbit Two-Port BiCMOS SRAM
A 4-ns 4K x 1-bit Two-Port BiCMOS SRAM
A 4ns 64KB BiCMOS SRAM Authors: Wingard, Stark, Horowitz
A 4-ns BiCMOS translation Lookaside Buffer Authors: Tamura, Yang, Wingard, Horowitz
Accuracy of Trace-Driven Simulationsof Multiprocessors (The) short version
Accuracy of Trace-Driven Simulationsof Multiprocessors (The)
Accurate Analysis of Array References
Hennessy, John Advances in Compiler Technology
Authors: Clyde Carpenter Mark Horowitz
Algorithms
Analysis of Cache Invalidation Patterns in Multiprocessors
Analysis of Cache Performance for Operating Systems and Multiprogramming
Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared Memory Multiprocessor
"Analysisof Parallelism and Deadlocks in Distributed-Time Logic Simulation
Analysis of Power Supply Networks in VSLI Circuits
An Analytical Cache Model Authors: Anant Agarwal, Mark Horowitz, John Hennessy
An Analytical Cache Model Version
Analyzing CMOS Power Supply Networks Using Ariel
Analyzing and Tuning Memory Performance in Sequential and … M. Martonosi
Anonymous one-time signatures and flexible untraceable electronic cash
Architectural and implementation tradeoffs in the design of multiple-context processors
Architectural and implementation tradeoffs in the design of multiple-context…
Architectural Tradeoffs in the design of MIPS
"Architecture of Field Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency
Array Data-Flow Analysis and its use in Array Privatization
Asymptotic Waveform Evaluation for Circuits with redundant DC Equations
ATUM: A New Technique for Capturing Address Traces Using Microcode
Automatic and Explicit Parallelization of N-Body Simulation
BiNMOS: A Basic Cell for BiCMOS Sea-of-Gates
The Benefits of Cllustering in Shared Address Space Multiprocessors: An Applications-Driven Investigation
Bipolar Circuit elements providing self-completion-indication
Russell Kao, Bob Alverson, Mark Horowitz, and Don Starck
Boosting Beyond Static Scheduling in a Superscalar Processor
Cache Coherence Directories for Scalable Multiprocessors
Cache Coherency Protocol Design Options for Large Scale Multiprocessors
Cache Invalidation Patterns in Shared-Memory Multiprocessors
Cache Performance of Operating System and Multiprogramming Workloads
The Cache Performance and Optimizations of Blocked Algorithms
Characteristics of Performance-Optimal Multi-Level Cache Hierarchies
Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation
Characterizing the Cache Performance and Synchronization Behavior of a Multiprocessor Operating System
Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System
Characterizing the Synchronization Behavior of Parallel Programs
Charging sharing models for MOS circuits
Charge-sharing models for switch-level simulation
Circuit Techniques for Large CSEA SRAMs
A Clocking Discipline for Two-Phase Digital Integrated Circuits
Coarse-Grain Parallel Programming in Jade
Code Generation using Tree Matching and Dynamic Programming
Code Optimization Across Procedures
Code Optimization of Pipeline Constraints
A Comparative Evaluation of Nodal and Supernodal Parallel Sparse Matrix Factorization: Detailed Simulation results
Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures
Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures
Comparison of the Rete and Treat Production Matchers for Soar (A Summary)
Comparative Evaluation of Latency Reducing and Tolerating Techniques
"Competitive Management of Distributed Shared Memory" Authors: D. Black, A. Gupta, W-D Weber
"Compilation of Single Assignment Languages: Analysis and Propositions" Authors: P. Schnorf . Ganapathi
"Compile-Time Copy Elimination" Authors: P. Schnorf, M. Ganapathi, JLH
Compile-time Partitioning Scheduling of Parallel Programs
Compiling Single Assignment Languages Authors: K. Gopinath and J.L. Hennessy
Uncorrected Preliminary Manuscript Computer Organization and Design: the Hardware/Software Interface
Computer Technology and Architecture: An Evolving Interaction
Consumer-based versus Producer-based Prefetch
"Cool: A Language for Parallel Programming" Authors: R. Chandra, A. Gupta, J. Hennessy
Copy Elimination with Abstract Interpretation
Copy Elimination in Functional Languages
The DASH prototype: implementation and performane
The DASH prototype: Logic Overhead and Performance
Data dependence and data-flow analysis of arrays
Data Locality and Load Balancing in COOL
Data Locality and Memory System Performance in the Parallel Simulation of Ocean Eddy Currents
Data Locality Optimizing Algorithm
Deriving Accurate Fault Models Author: John Michael Acken
Design and Analysis of DASH: A scalable directory-based multiprocessor
"Design and Clocking of VLSI multipliers" M. R. Santoro
"Design of a Digital Audio Input Output Chip"
Design and Evaluation of Compiler Optimizations for Scalable Shared Address Space Machines
Design and Evaluation of a Compiler Algorithm for Prefetching
Design of a High-Performance Cache-Controller: a case study in asynchronous synthesis
Design of a high-performance VLSI Processor
Design and Implementation of an Optimizing Compiler for Single Assignment Language
"Design of the Stanford DASH Multiprocessor"
The Design and Testing of MIPS-X P.Chow and M. Horowitz
The Design Verification Testing of MIPS
"Designing High-Performance Digital Circuits Using Wave Pipelining Authors: Wong, DeMicheli, Flynn
Detecting Violations of Sequential Consistency Author: Gharachorloo, K. Gibbons, P.
"The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor" Authors: D. Lenoski, J. Laudon, et al
Dynamic Pointer Allocation for Scalable Cache Coherence Directories Author: Simoni, R. /Horowitz, M.
Editing Graphical Objects Using Procedural Representations Author: Paul Asente
The Effect of Logic Block Complexity on Area of Programmable Gate Arrays Authors: Rose, Francis, Chow, Lewis
Effectiveness of Trace Sampling for Performance Debugging Tools Martonosi, M. Gupta, A, and Anderson T.
Effective Copy Elimination in Single Assignment Languages Author: Schnorf, Peter et al.
Efficient Block-Oriented Approach to Parallel Sparse Cholesky Factorization (An)
Efficient and Exact Data Dependence Analysis
"Efficient Generation of Test Patterns Using Boolean Satisfiability" (thesis) Author: T. Larrabee
Efficient Moment-Based Timing Analysis for Variable Accuracy Switch Level Simulation
Efficient Moment-Based Timing Analysis for Variable Accuracy Switch Level Simulation
Efficient Scheduling on Multiprogrammed Shared-Memory… A. Tucker
Efficient Sparse Matrix Factorization on High-Performance Workstations -- Exploiting the Memory Hierarchy
Efficient Superscalar Performance Through Boosting Smith, Horowitz, Lam, M.
Eliminating Redundant DC Equations for Asymptotic Waveform Evaluation
Emitter Follower-Based Drivers for Large ECL loads
An Empirical Investigation of the Effectiveness and Limitations of Automatic Parallelization
An Empirical Comparison of the Kendall Square Research KSR-1 and Stanford DASH Multiprocessors Authors: Singh, JP et al
Equilibrium Detection and Temperature Measurement of Simulated Annealing Placements
Torrellas and Hennessy
Evaluating Interprocedural Code Optimization Techniques
Evaluating the Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors
Evaluating the Memory Overhead Required for COMA Architectures
An Evaluation of the Chandy-Misra-Byrant Algorithm for Digital Logic Simulation
Evaluation of Directory Schemes for Cache Coherence
Experiences Implementing a Parallel ATMS on a Shared-Memory Multiprocessor
Eploiting the Memory Hierarchy in Sequential and Parallel Sparse Cholesky Factorization
Exploiting Variable Grain Parallelism at Runtime
Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results Authors: Weber, Gupta
Fast Functional Simulation: An Incremental Approach
Fast Operating System Simulation
"Fast Sparse Matric Factorization on Modern Workstations" Authors: E. Rothberg, A. Gupta
P. A. Eichenberger Thesis (original copy)
Fast Symbolic Layout Transition for Custom VLSI Integrated Circuits
FIAT: A Framework for Interprocedural Analysis and Transformation
Finding and Exploiting Parallelism in an Ocean Ocean Simulation Program: Experience, Results, and Implications
Flexible Netlist Processing Via Pattern Matching
The Formal Definition of a Real-Time Language
General Compiled Electrical Simulation Authors: Weise, Seligman
Generalization in Connectionist Network that Realize Boolean Functions Authors: K.A. Ruyser, M. A. Horowitz
Generating Incremental VLSI Compaction Spacing Constraints Clyde Carpenter Mark Horowitz
Hardware C- A Language for Hardware Design , Authors: Ku. DeMicheli
Hardware-Software Co-Design
Hardware/Software Tradeoffs for Increased Performance Authors: J. Hennessy, N. Jouppi, et al.
Hercules - A System for High-level synthesis
The Hermod Behavioral Synthesis System Authors: Odani, Hwang, Blank, Rokicki
Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors
Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors
High Performance Microprocessor Architectures
High Speed BiCMOS Memories
Impact of Operating System scheduling policies and synchronization methods on the performance of parallel applications
The Implementation of MIPS
"Implementing a Directory-Based Cache Consistency Protocol" Author Richard Simoni
Implications of Hierarchical N-body Techniques for Multiprocessor Architecture
Implications of Hierarchical N-body Techniques for Multiprocessor Architecture
Implications of Non-Binary Sized Instructions
Improved Models for Switch-level simulation Author: Chorng-Yeong Chu
Improving Locality and Parallelism in Nested Loops
Incremental Circuit Extraction
Incremental -in-Time Algorithm for Digital Simulation
Efficiency Considerations in Program Synthesis: A Knowledge-Based Approach
File Access Performance of Diskless Workstations
Incremental Tools for the Design and Verification of VLSI Circuits
Incremental VLSI Compaction Author: Clyde W. Carpenter
Instruction Selection by Attributed Parsing
Integrating Concurrency and Data Abstraction in the COOL Parallel Programming Language
Integrated Pin Electronics for VLSI Functional Testers
Integrating Concurrency and Data Abstraction in a Parallel Programming Language
Integrating Concurrency and Data Abstraction in a Parallel Programming Language
Integrating Scalar Optimization and Parallelization
Integration of Message Passing and Shared Memory
Interleaving: A Multithreading Technique Targetting Multiprocessors and Workstations
Interprocedural Analysis Useless for Code Optimization
Interprocedural Analysis vs. Procedure Integration
Interprocedural Optimization: Experimental Results
"Interval Methods for Distributed Simulation Systems" Authors: A.R.W. Todesco
"IRSIM: An Incremental MOS Switch-Level Simulator"
John Hennessy A Language for Microcode Description and Simulation in VLSI
Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines Rings
Limits of Control Flow on Parallelism
Limits on Multiple Instruction Issue Authors: M. Smith, M. Johnson, M. Horowitz
LISP
LISP
LISP on a Reduced-Instruction-Set Processor: Characterization and Optimization
Load Balancing and Data Locality in Hierarchical N-Body Methods
LocusRoute: A Parallel Global Router for Standard Cells
Logic Minimization, Placement Routing in SWAMI
Mable: A Technique for Efficient Machine Stimulation
Mable: A Technique for Efficient Machine Stimulation
MAGIC: the Beta Release UCB-EECS
Making Effective Use of Shared-Memory Multiprocessors: The Process Control Approach
Measurement, Analysis and Improvement of the Cache Behavior of a Shared Data in Cache Coherent Multiprocessors"
Measurement and Evaluation of the MIPS Architecture and Processor
Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors
"Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors"
Memory-Reference Characteristics of Multiprocessor Applicationa under MACH
MemSpy: Analyzing Memory System Bottlenecks in Programs
"A Methodology for Modeling Inter-processor Traffic in Shared Memory Multiprocessors"
MIPS: A Microprocessor Architecture
MIPS: A VLSI Processor Architecture
MIPS-X: A 20 MIPS Peak, 32-bit microprocessor with on-chip cache
The MIPS-X External Cache Processor: Functionality and I/O
MIPS-X: The External Interface
MIPS-X: Instruction Set and Programmer's Manual
The MIPSX Microprocessor Horowitz, Chow
Modeling the Performance of Limited Pointers Directories for Cache Coherence
MTOOL: an Integrated System for Performance Debugging Shared Memory Multiprocessor Applications
MTOOL: A Method for Isolating Memory Bottlenecks in Shared Memory Multiprocessor Programs
Multi-Level Logic Array Synthesis Author: Rowen, Christopher
Multiprocessor Cache Memory Performance: Characterization and Optimization
Multiprocessor Cache Analysis Using ATUM
Multiprocessor RISCS: Design Issues R. H. Katz, et al.
MultiTitan-Four Architecture Papers Digital, West. Res. Lab.
Multis: A New Class of Multiprocessor Computers By: Bell
The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range. Author: F. McMahon
Multiprocessor Performance Debugging and Memory Bottlenecks
Multiprocessor RISCS: Design Issues Initial Analyses
Multiprocessor Simulation: Achieving Accuracy, Efficiency, and Flexibility
Multiprocessor Simulation and Tracing Using Tango
"Nondeterminism and Unification in Log-Scheme: Integrating Logic and Functional Programming"
On-Chip Instruction Caches for High Performance Processors Anant Agarwal, Paul Chow, Mark Horowitz
Organization and VLSI Implementation of MIPS
An Overview of the MIPS-X-MP Project #86-300 John Hennessy Mark Horowitz
Overview and Status of the Stanford DASH Multiprocessor
Overview of the Stanford U-Code Compiler System
Overview of Work in VLSI Systems and Software Area
A Parallel Adaptive Fast Multipole Method
The Parallel Decomposition and Implementation of an Integrated Circuit Global Router
"Parallel Distributed-Time Logic Simulation" Authors: L. Soule, A. Gupta
Parallel Global Routing for Standard Cells Author: Rose
Parallel Hierarchical N-Body Methods and Their Implications for Multiprocessors
Parallelizing Compilers: Implementation and Effectiveness
Parallel ICCG on a Hierarchical Memory Multiprocessor-- Addressing the Triangular Solve Bottleneck
Parallel Implementation of OPS5 on the Encore Multiprocessor: Results Analysis Authors: Gupta, Tambe, Kalp, Forgy, Newell
Parallel Logic Simulation: an Evaluation of Centralized-Time and Distributed-Time Algorithms
Parallel Logic Simulation on General Purpose Machines
Parallel OPS5 on the Encore Multimax Authors: Gupta, Forgy, Kalp, Newell, Tambe
"Parallelizing the Simulation of Ocean Eddy Currents" Authors:J. P. Singh J. L. Hennessy
Partitioning and Scheduling Parallel Programs for Execution on Multiprocessors Author: Vivek Sarkar
Partitioning parallel Programs for Macro-Dataflow
PASCAL and Pascal* Compiler Systems Author: Hennessy, J.
Pascal*: A Pascal Based Systems programming language
The Performance Advantages of Integrating Block Data Transfer in Cache-Coherent Multiprocessors
The Performance Advantages of Integrating Message-Passing in Cache-Coherent Multiprocessors
Performance Debugging Shared Memory Multiprocessor Programs with MTOOL
Performance-Directed Memory Hierarchy Design Author: Steven A. Przybylski
Performance Evaluation of Hybrid Hardware and Software Distributed Shared Memory Protocols
Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors
Performance Impact of Data Reuse in Parallel Dense Cholesky Factorization
The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor
David Marple Performance Optimization of Digital VLSI Circuits
Performance of Update Algorithms for Replicated Data in a Distributed Database
The Priority-Based Coloring Approach
Procedure Merging with Instruction Caches
Process Control and Scheduling Issues for Multiprogrammed Shared-Memory Multiprocessors
Program Analysis and Optimization for Machines with Instruction Cache
Programming for Different Memory Consistency Models
McFarland
the Programming Language Rascal Author: Paulson, L.
Performance Tradeoffs in Cache Design Authors: Przyblysky, Horowitz, Hennessy
Piecewise Linear Models for Rsim
Piecewise Linear Models for Switch-Level Simulation
Precise Delay Generation Using Coupled Oscillators J. Maneatis thesis
A Portable Machine-Independent Global Optimizer-- Design and Measurements Author: Chow, F.
Postpass Code Optimization of Pipeline Constraints
Precise Delay Generation Using Coupled Oscillators J. M
A Programming and Problem-Solving Seminar
Qualifying Examinations in Computer Science 1965-1978 edited by Frank M. Liang
Rationale, Design and Performance of the Hydra Multiprocessor K. Olukotun, et al.
REDS: Resistance Extraction for Digital Simulation
Reducing the Cost of Branches McFarling, S. Hennessy, J.
"Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes"
Reducing Overhead in Counter-Based Execution Profiling
Research in VLSI Systems Systems Design and Architecture
Research in VLSI Systems Technical Progress Report
Resumes of Graduate Students
"Rounding Algorithms for IEEE Multipliers" Authors: M. Santoro, G. Bewick, M. Horowitz
The S-1 Multiprocessor Finnel
Reverse Synthesis Compilation for Architectural Research
RISC Architectures P. Chow, J. Hennessy
RISC-Based Processors: Concepts and Prospects Author: John Hennessy
Research in VSLI Systems Technical Progress Report
Retargetable Compiler Code Generation Author: M. Ganapathi, C. Fischer, J. Hennessy
SAL: A Single Assignment Language for Parallel Algorithms
Scalable Directories for Cache-Coherent Shared Memory Multiprocessors
Scalable Directory Schemes for Cache Coherence
Scalar Privatization: Algorithm and Effect on Compiler Detected
Scaling Parallel Programs for Multiprocessors: Methodology and Examples
A Self-Timed Chip for Division Authors: Williams, Horowitz, et al
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)
A Self-Timed SRT Diversion Chip Authors: Williams, T., Horowitz, M., et al.
Semantic Foundations of Jade
"Semantic Predicates in Parser Generators" Author: M. Ganapathi
Shared Memory vs. Message Passing Architectures: An Application Based Study Authors: Martonosi, Gupta
A Short Guide to MIPS Assembly Instructions Authors: Gross, T. Gill, J.
Signal Delay in RC Tree Netowkrs Horowitz, M.
A Simple and Efficient Implementation Approach for Single Assignment Language (Technical Summary)
A Simple Interprocedural Register Allocation Algorithm and its Effectiveness for LISP
A Single Chip LSI High-Speed Functional Tester Authors: J. Miyamoto M.A. Horowitz
SLIM: A Simulation Implementation Language for VLSI Microcode
Soft Configurable Water Scale integration: Design, Implementation, and Yield Analysis. Author: M. Blatt
Specifying System Requirements for Memory Consistency Models
Spectral Lower-Bound Techniques… Brandman
A Spectral Lower-Bound Technique for the Size of Decision Trees and Two-Level Circuits
"SPIM: A Pipelined 64 x 64 bit Iterative Multiplier" Authors: M. Santoro, M.A. Horowitz
SPLASH: Stanford Parallel Applications for Shared-Memory
SPLASH: Stanford Parallel Applications for Shared-Memory
SPUR: A VLSI Multiprocessor Workstation M. Hill et al
SRT Division Diagrams and Their Usage… Williams/Horowitz
Sail
Monitor Command Manual
Booklet of Viewgraphs Stanford Computer Forum
Stanford U-Code
A Static Ram as a Fault Model Evaluator John Acken Mark Horowitz
Streams in a Single-Assignment Language
STRIP: A Self-Timed RISC Processor
Study of Compiler Detection of Loop-Level Parallelism Technical Summary (A)
The Stanford DASH Multiprocessor
Suficient System Requirements for Supporting the PLPC Memory Model
Suitability of Message Passing Computers for Implementing Production Systems
Summary of MIPS Instructions
"Super-Scalar Processor Design" Author: William M. Johnson (thesis)
Support for Speculative Execution in High-Performance Processors
Computer Science Department
Tau Epsilon Chi A System for technical Text
Tau Epsilon Chi A System for technical Text
Tau Beta Pi Teaching Survey
Series 2. Papers Accession ARCH-2017-269
Professional (CS) talks and slides for talks delivered by Hennessy and collaborators; subjects include MIPS, ACAST, LISP, MCP, RISC Architecture
MIPS Microprocessor
Professional (CS) talks and slides (chiefly transparencies) for talks delivered by Hennessy and collaborators; subjects include HPCC, Symbolic debugging, RISC architecture, DAC, CS Laboratory overviews, MTOOL, VLSI, Distributed computing, Control compilation, ARPA
ISCA (International Symposium on Computer Architecture) slide presentations, correspondence; ASCI (Accelerated Strategic Computing Initiative) Stanford proposal; slide presentations; various FLASH presentations; School of Engineering Tentative Fundraising Priorities FY99-04; DARPA ITO PI Meeting presentation slides 1996; ISAT 1991 presentation slides; DASH slides; IEEE Standards; High Performance Computing slides; Information Technology Office Programs and Strategy; School of Engineering Goals and Directions slides
Project documentation, correspondence, proposals, and reports on SWAMI, ASTEC, ARPA/DARPA, S-1 and U-Code compiler programs; Publisher correspondence for 1990 computer architecture textbook
3 BASF L750 Chrome Video Cassettes labeled 'MIPS-1,' 'MIPS-2,' and "4/22, 4/27"; VHS, "UCLA Computer Science Department Distinguished Lecturer Series, 1992-1993"; VHS, "Dr. William Clinger," 10/27/87, review copy"; VHS, John Hennessy, "Scalable Multiprocessors and the DASH Approach," 4.10.1992; VHS, Stanford University "Near West Campus"; VHS, "Future Directions in Computer Architecture," June 18, 1990; VHS tapes 1, 2, and 3, John Hennessy, "RISC Architectures: Fundamentals, Design Alternatives and Futures?", 7.5.1989; VHS, Hennessy, "Scalable Shared-Memory Multiprocessors and the DASH Approach," 6.19.1990; VHS, Hennessy "Wilkes, WK #0115," 10.3.95; VHS Hennessey, "Scalable Shared Memory Multiprocessors and the Stanford DASH Machine," 11.13.91; VHS, Justin Rattner, "Programming Techniques for Concurrent Supercomputers," September 2, 1988; VHS, Harold Stone, "Specializing in Parallel with a Combining Network," 10.9.1987; VHS, Seymour Cray, "What's All This About Gallium Arsenide," 11.15.1988; VHS, "George Taylor, MIPS. Profs. Allison/Wharton," 2.21.1990; VHS, EE 380 Allison and Wharton, 9.25.91; VHS, Tilak Agerwala, "Parallel Processing," April 28, 1989; VHS, "VC32 RISC," 10.26.1989; VHS, "John Hennessy Graphics", 3.27.1992; two tapes, Stanford Instructional Television Network, TV station format
Published and unpublished technical reports and papers by Hennessy and colleagues, primarily on MIPS-X project, with associated correspondence
Articles and reports kept by Hennessey, some written by him. Reports written by Hennessey may also include drafts and other supplementary materials . Research often related to MIPS
"confidential" corporate reports (1987); MIPS Computer Systems documentation; SIGPLAN- Special Interest Group on Programming Languages; IEEE Standards Department Appeal Committee Report for Appeal #1754 (rejected) (1994); Draft Standard for a 32-bit Microprocessor Architecture (1993)
9 binders + 4 folders: mostly Computer Science and Telecommunications Board meeting agendas ; Committee on Academic Careers for Experimental Computer Sciences
Computer Science and Technology Board, materials from a number of years beginning in the late 1980s; course materials; an envelope of photos; two 3M data cartridges; Stanford Compiler Group SUIF Compiler System handbook
ASTEC II; NSF proposal (rejected): Advanced Computer Architecture and System Tech (ACAST); STC Proposal/Correspondence w/ David J. Kuck (UIUC) (1990); DARPA Reports 1988, 1989.
Transparencies. Handouts for 240B, RISC Architectures, overlay/slides, articles,
Conference, workshop, and association briefing materials (IEEE, ISCA, SIGARCH, VLSI, etc.); drafts and preprints of papers by Hennessy and others; technical reports by Hennessy and others
Miscellaneous stuff, electrical engineering docs, correspondence, World Economic Forum Industry Summit, SchoolEng publications, correspondence,
Articles and technical reports, by Hennessy and others
Industrial contracts; conference and workshop materials
Gates Computer Science Building and Geology Classroom Blueprints
FLASH Project: LSI, Intel FLASH Non-disclosure agreements; articles; Army Award-Sponsored Projects; Qtrly Reports; Darpa 2/20/97;
Videotapes (VHS & 2 Beta): The Distinguished Lecture Series; Commercial Lectures; Corporate tapes; \non-labeled tapes; prof's course tapes
Articles and technical reports, by Hennessy and others (Dataflow research projects; UCI Dataflow Architecture Project; Advanced Research Projects Agency; ACM Transactions on Programming Language and Systems; National Science Foundation; IBM; Computer Science Department; Science Research Council; Palo Alto Research Center;Institute for Electrical Engineers; various universities)
Presentation and meeting materials (Advisory Board Council Meetings; HPCC Committee; Advanced Reserach Projects Agency; Defense Advanced Research Project Agency Inforamtion Science and Technology Office; Workshop Series on High Performance Computing and Communications; National Center for Biotechnology Information; Computer Science and Telecommunications Board; ISAT Executive Committee)
Videotapes (29 VHS): Distinguished Lecture Series, Volume II; The Distinguished Lecture Series IV; The Distinguished Lecture Series VI; Selections from Hot Chips V; LEaders in Computer Science & Electrical Engineering
Notes and course materials; transparencies; historical talk slides; EE281 Microcomputer Lab [First class he taught]; MIPS related slides
Videotapes (29 VHS): Distinguished Lecture Series, Volume II; The Distinguished Lecture Series IV; The Distinguished Lecture Series VI; Selections from Hot Chips V; Leaders in Computer Science & Electrical Engineering
"Bugs" caught by Michael Jones. Includes letter from Morgan Kaufman Publishers. ARCH-2023-002