Guide to the John L. Hennessy Personal Papers SC1362

Jenny Johnson
Department of Special Collections and University Archives
January 2019
Green Library
557 Escondido Mall
Stanford 94305-6064
specialcollections@stanford.edu

Note

This encoded finding aid is compliant with Stanford EAD Best Practice Guidelines, Version 1.0.


Language of Material: English
Contributing Institution: Department of Special Collections and University Archives
Title: John L. Hennessy Personal Papers
creator: Hennessy, John L.
Identifier/Call Number: SC1362
Physical Description: 10.5 Linear Feet (7 cartons)
Date (inclusive): 1968-1998
Language of Material: English
Physical Location: Special Collections and University Archives materials are stored offsite and must be paged 36-48 hours in advance. For more information on paging collections, see the department's website: http://library.stanford.edu/spc .
Physical Location: Special Collections and University Archives materials are stored offsite and must be paged at least 36 hours in advance.

Conditions Governing Use

While Special Collections is the owner of the physical and digital items, permission to examine collection materials is not an authorization to publish. These materials are made available for use in research, teaching, and private study. Any transmission or reproduction beyond that allowed by fair use requires permission from the owners of rights, heir(s) or assigns. See: http://library.stanford.edu/spc/using-collections/permission-publish

Preferred Citation

[identification of item], John L. Hennessy Personal Papers (SC1362). Department of Special Collections and University Archives, Stanford University Libraries, Stanford, Calif.

Biographical / Historical

John L. Hennessy is Director of Knight-Hennessy Scholars, the largest fully endowed graduate-level scholarship program in the world. He is Chairman of the Board of Alphabet and serves on the Board of Directors for Cisco Systems and the Board of Trustees for Gordon and Betty Moore Foundation. Formerly the tenth President of Stanford University, he is also a computer scientist who co-founded MIPS Computer Systems and Atheros Communications. He and Dave Patterson were awarded the ACM A.M. Turing Prize for 2017.

Scope and Contents

The materials consist of publications, research and teaching files, professional files and correspondence, and audiovisual materials.

Subjects and Indexing Terms

College administrators.
Computer scientists.
Computer science -- Research
Hennessy, John L.
Hennessy, John L.

 

Papers Accession ARCH-2017-269

 

Publications

box 1, folder 1

Computer Architecture a Quantitative Approach 1996

box 1, folder 2

Maryland 1994 Mar

box 1, folder 3

Flash Slides ARPA 1993 Nov

box 1, folder 4

DASH (1 of 2)

box 1, folder 5

DASH (2 of 2)

box 1, folder 6

EE182: Computer Architecture and Organization Information Sheet 1993-1992

box 1, folder 7

Computer Architecture a Quantitative Approach 1996

box 1, folder 8

Tau Beta Pi Teaching Survey Winter Quarter 1978-1979

box 1, folder 9

Tau Beta Pi Teaching Survey Spring Quarter 1978-1979

box 1, folder 10

Tau Beta Pi Teaching Survey Autumn Quarter 1976-1977

box 1, folder 11

Tau Beta Pi Engineering Course Evaluations Spring Quarter 1981

box 1, folder 12

Tau Beta Pi Engineering Course Evaluations Autumn Quarter 1980

box 1, folder 13

Tau Beta Pi Engineering Course Evaluations Winter Quarter 1981

box 1, folder 14

Endowed Professorships Directorships at Stanford University 1992 Feb 10

box 2, folder 1

Booklet of Abstracts and Viewgraphs Stanford Computer Forum 1984 Feb

box 2, folder 2

DEC System -10/20 Hardware Manual 1977

box 2, folder 3

CSL, Abstracts 1968-1992

box 2, folder 4

A 160nS 54bit CMOS Division Implementation using Self-timing and symmetrically overlapped SRT stages

box 2, folder 5

A 4 nsec 4Kxlbit Two-Port BiCMOS SRAM 1988

box 2, folder 6

A 4-ns 4K x 1-bit Two-Port BiCMOS SRAM 1998

box 2, folder 7

A 4ns 64KB BiCMOS SRAM Authors: Wingard, Stark, Horowitz

box 2, folder 8

A 4-ns BiCMOS translation Lookaside Buffer Authors: Tamura, Yang, Wingard, Horowitz

box 2, folder 9

Accuracy of Trace-Driven Simulationsof Multiprocessors (The) short version

box 2, folder 10

Accuracy of Trace-Driven Simulationsof Multiprocessors (The) 1992

box 2, folder 11

Accurate Analysis of Array References 1992 Sep

box 2, folder 12

Hennessy, John Advances in Compiler Technology

box 2, folder 13

Authors: Clyde Carpenter Mark Horowitz

box 2, folder 14

Algorithms

box 2, folder 15

Analysis of Cache Invalidation Patterns in Multiprocessors 1988

box 2, folder 16

Analysis of Cache Performance for Operating Systems and Multiprogramming 1987 May

box 2, folder 17

Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared Memory Multiprocessor

box 2, folder 18

"Analysisof Parallelism and Deadlocks in Distributed-Time Logic Simulation 1989

box 2, folder 19

Analysis of Power Supply Networks in VSLI Circuits 1991 Mar

box 2, folder 20

An Analytical Cache Model Authors: Anant Agarwal, Mark Horowitz, John Hennessy 1986

box 2, folder 21

An Analytical Cache Model Version 1988 Apr 25

box 2, folder 22

Analyzing CMOS Power Supply Networks Using Ariel 1988

box 2, folder 23

Analyzing and Tuning Memory Performance in Sequential and … M. Martonosi 1994 Jan

box 2, folder 24

Anonymous one-time signatures and flexible untraceable electronic cash 1988

box 2, folder 25

Architectural and implementation tradeoffs in the design of multiple-context processors 1992

box 2, folder 26

Architectural and implementation tradeoffs in the design of multiple-context… 1994 Sep

box 2, folder 27

Architectural Tradeoffs in the design of MIPS 1985 Oct

box 2, folder 28

"Architecture of Field Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency

box 2, folder 29

Array Data-Flow Analysis and its use in Array Privatization 1993

box 2, folder 30

Asymptotic Waveform Evaluation for Circuits with redundant DC Equations 1991 May

box 2, folder 31

ATUM: A New Technique for Capturing Address Traces Using Microcode

box 2, folder 32

Automatic and Explicit Parallelization of N-Body Simulation 1991 Mar

box 2, folder 33

BiNMOS: A Basic Cell for BiCMOS Sea-of-Gates

box 2, folder 34

The Benefits of Cllustering in Shared Address Space Multiprocessors: An Applications-Driven Investigation

box 2, folder 35

Bipolar Circuit elements providing self-completion-indication 1989

box 2, folder 36

Russell Kao, Bob Alverson, Mark Horowitz, and Don Starck

box 2, folder 37

Boosting Beyond Static Scheduling in a Superscalar Processor 1990 July

box 2, folder 38

Cache Coherence Directories for Scalable Multiprocessors 1992 Oct

box 2, folder 39

Cache Coherency Protocol Design Options for Large Scale Multiprocessors

box 2, folder 40

Cache Invalidation Patterns in Shared-Memory Multiprocessors

box 2, folder 41

Cache Performance of Operating System and Multiprogramming Workloads

box 2, folder 42

The Cache Performance and Optimizations of Blocked Algorithms 1991

box 2, folder 43

Characteristics of Performance-Optimal Multi-Level Cache Hierarchies

box 2, folder 44

Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation 1989 Jun

box 2, folder 45

Characterizing the Cache Performance and Synchronization Behavior of a Multiprocessor Operating System 1992 Jan

box 2, folder 46

Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System 1992

box 2, folder 47

Characterizing the Synchronization Behavior of Parallel Programs 1988 July

box 2, folder 48

Charging sharing models for MOS circuits 1986 Nov

box 2, folder 49

Charge-sharing models for switch-level simulation

box 2, folder 50

Circuit Techniques for Large CSEA SRAMs 1992

box 2, folder 51

A Clocking Discipline for Two-Phase Digital Integrated Circuits 1983 Jan

box 2, folder 52

Coarse-Grain Parallel Programming in Jade

box 2, folder 53

Code Generation using Tree Matching and Dynamic Programming 1989 Oct

box 2, folder 54

Code Optimization Across Procedures 1989 Feb

box 2, folder 55

Code Optimization of Pipeline Constraints 1983 Dec

box 2, folder 56

A Comparative Evaluation of Nodal and Supernodal Parallel Sparse Matrix Factorization: Detailed Simulation results 1992 May

box 2, folder 57

Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures 1991 Nov 12

box 2, folder 58

Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures 1992 May

box 3, folder 1

Comparison of the Rete and Treat Production Matchers for Soar (A Summary) 1988

box 3, folder 2

Comparative Evaluation of Latency Reducing and Tolerating Techniques 1991 Mar

box 3, folder 3

"Competitive Management of Distributed Shared Memory" Authors: D. Black, A. Gupta, W-D Weber 1989

box 3, folder 4

"Compilation of Single Assignment Languages: Analysis and Propositions" Authors: P. Schnorf . Ganapathi 1989 Nov

box 3, folder 5

"Compile-Time Copy Elimination" Authors: P. Schnorf, M. Ganapathi, JLH 1993 Apr

box 3, folder 6

Compile-time Partitioning Scheduling of Parallel Programs

box 3, folder 7

Compiling Single Assignment Languages Authors: K. Gopinath and J.L. Hennessy

box 3, folder 8

Uncorrected Preliminary Manuscript Computer Organization and Design: the Hardware/Software Interface 1997

box 3, folder 9

Computer Technology and Architecture: An Evolving Interaction

box 3, folder 10

Consumer-based versus Producer-based Prefetch 1994 Mar

box 3, folder 11

"Cool: A Language for Parallel Programming" Authors: R. Chandra, A. Gupta, J. Hennessy 1989 Oct

box 3, folder 12

Copy Elimination with Abstract Interpretation

box 3, folder 13

Copy Elimination in Functional Languages 1988 Nov

box 3, folder 14

The DASH prototype: implementation and performane 1992

box 3, folder 15

The DASH prototype: Logic Overhead and Performance 1993

box 3, folder 16

Data dependence and data-flow analysis of arrays 1992

box 3, folder 17

Data Locality and Load Balancing in COOL 1993

box 3, folder 18

Data Locality and Memory System Performance in the Parallel Simulation of Ocean Eddy Currents 1991 Aug

box 3, folder 19

Data Locality Optimizing Algorithm 1991

box 3, folder 20

Deriving Accurate Fault Models Author: John Michael Acken 1988 Oct

box 3, folder 21

Design and Analysis of DASH: A scalable directory-based multiprocessor 1992 Feb

box 3, folder 22

"Design and Clocking of VLSI multipliers" M. R. Santoro 1989 Oct

box 3, folder 23

"Design of a Digital Audio Input Output Chip"

box 3, folder 24

Design and Evaluation of Compiler Optimizations for Scalable Shared Address Space Machines 1994

box 3, folder 25

Design and Evaluation of a Compiler Algorithm for Prefetching 1992

box 3, folder 26

Design of a High-Performance Cache-Controller: a case study in asynchronous synthesis 1993 Apr

box 3, folder 27

Design of a high-performance VLSI Processor 1983 Feb

box 3, folder 28

Design and Implementation of an Optimizing Compiler for Single Assignment Language 1990 Nov

box 3, folder 29

"Design of the Stanford DASH Multiprocessor" 1989 Dec

box 3, folder 30

The Design and Testing of MIPS-X P.Chow and M. Horowitz

box 4, folder 1

The Design Verification Testing of MIPS

box 4, folder 2

"Designing High-Performance Digital Circuits Using Wave Pipelining Authors: Wong, DeMicheli, Flynn

box 4, folder 3

Detecting Violations of Sequential Consistency Author: Gharachorloo, K. Gibbons, P. 1991 May

box 4, folder 4

"The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor" Authors: D. Lenoski, J. Laudon, et al 1989 Dec

box 4, folder 5

Dynamic Pointer Allocation for Scalable Cache Coherence Directories Author: Simoni, R. /Horowitz, M. 1991 Aug

box 4, folder 6

Editing Graphical Objects Using Procedural Representations Author: Paul Asente 1987 Oct

box 4, folder 7

The Effect of Logic Block Complexity on Area of Programmable Gate Arrays Authors: Rose, Francis, Chow, Lewis

box 4, folder 8

Effectiveness of Trace Sampling for Performance Debugging Tools Martonosi, M. Gupta, A, and Anderson T. 1993 July

box 4, folder 9

Effective Copy Elimination in Single Assignment Languages Author: Schnorf, Peter et al. 1991

box 4, folder 10

Efficient Block-Oriented Approach to Parallel Sparse Cholesky Factorization (An) 1992 July

box 4, folder 11

Efficient and Exact Data Dependence Analysis 1991 Jun

box 4, folder 12

"Efficient Generation of Test Patterns Using Boolean Satisfiability" (thesis) Author: T. Larrabee 1990 Feb

box 4, folder 13

Efficient Moment-Based Timing Analysis for Variable Accuracy Switch Level Simulation 1991 Apr

box 4, folder 14

Efficient Moment-Based Timing Analysis for Variable Accuracy Switch Level Simulation 1991 Apr

box 4, folder 15

Efficient Scheduling on Multiprogrammed Shared-Memory… A. Tucker 1994 Jan

box 4, folder 16

Efficient Sparse Matrix Factorization on High-Performance Workstations -- Exploiting the Memory Hierarchy 1990 Sep 12

box 4, folder 17

Efficient Superscalar Performance Through Boosting Smith, Horowitz, Lam, M.

box 4, folder 18

Eliminating Redundant DC Equations for Asymptotic Waveform Evaluation 1993 Apr 19

box 4, folder 19

Emitter Follower-Based Drivers for Large ECL loads 1993 May 19-21

box 4, folder 20

An Empirical Investigation of the Effectiveness and Limitations of Automatic Parallelization 1991 Apr

box 4, folder 21

An Empirical Comparison of the Kendall Square Research KSR-1 and Stanford DASH Multiprocessors Authors: Singh, JP et al 1993 Nov 15-19

box 4, folder 22

Equilibrium Detection and Temperature Measurement of Simulated Annealing Placements 1988 May

box 4, folder 23

Torrellas and Hennessy

box 4, folder 24

Evaluating Interprocedural Code Optimization Techniques 1991 Feb

box 4, folder 25

Evaluating the Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors 1992 Aug

box 4, folder 26

Evaluating the Memory Overhead Required for COMA Architectures 1994 Apr

box 4, folder 27

An Evaluation of the Chandy-Misra-Byrant Algorithm for Digital Logic Simulation 1992 Jan

box 4, folder 28

Evaluation of Directory Schemes for Cache Coherence 1988

box 4, folder 29

Experiences Implementing a Parallel ATMS on a Shared-Memory Multiprocessor 1989

box 4, folder 30

Eploiting the Memory Hierarchy in Sequential and Parallel Sparse Cholesky Factorization 1992 Nov

box 4, folder 31

Exploiting Variable Grain Parallelism at Runtime 1988 July

box 4, folder 32

Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results Authors: Weber, Gupta 1988 Nov 16

box 4, folder 33

Fast Functional Simulation: An Incremental Approach 1988 July

box 4, folder 34

Fast Operating System Simulation 1994 Oct

box 4, folder 35

"Fast Sparse Matric Factorization on Modern Workstations" Authors: E. Rothberg, A. Gupta 1989 Oct 2

box 4, folder 36

P. A. Eichenberger Thesis (original copy) 1986 Apr

box 4, folder 37

Fast Symbolic Layout Transition for Custom VLSI Integrated Circuits 1986 Apr

box 4, folder 38

FIAT: A Framework for Interprocedural Analysis and Transformation 1994

box 4, folder 39

Finding and Exploiting Parallelism in an Ocean Ocean Simulation Program: Experience, Results, and Implications

box 4, folder 40

Flexible Netlist Processing Via Pattern Matching 1993

box 4, folder 41

The Formal Definition of a Real-Time Language 1978 July

box 4, folder 42

General Compiled Electrical Simulation Authors: Weise, Seligman 1989

box 4, folder 43

Generalization in Connectionist Network that Realize Boolean Functions Authors: K.A. Ruyser, M. A. Horowitz

box 4, folder 44

Generating Incremental VLSI Compaction Spacing Constraints Clyde Carpenter Mark Horowitz 1987

box 4, folder 45

Hardware C- A Language for Hardware Design , Authors: Ku. DeMicheli 1988

box 4, folder 46

Hardware-Software Co-Design 1993 Oct

box 4, folder 47

Hardware/Software Tradeoffs for Increased Performance Authors: J. Hennessy, N. Jouppi, et al. 1983 Jan

box 4, folder 48

Hercules - A System for High-level synthesis 1988

box 4, folder 49

The Hermod Behavioral Synthesis System Authors: Odani, Hwang, Blank, Rokicki 1989

box 4, folder 50

Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors 1992 May

box 4, folder 51

Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors 1993 Apr

box 4, folder 52

High Performance Microprocessor Architectures 1989-1990

box 4, folder 53

High Speed BiCMOS Memories 1994 Dec

box 4, folder 54

Impact of Operating System scheduling policies and synchronization methods on the performance of parallel applications 1990 Sep 19

box 4, folder 55

The Implementation of MIPS 1984 Aug

box 4, folder 56

"Implementing a Directory-Based Cache Consistency Protocol" Author Richard Simoni 1990 Mar

box 4, folder 57

Implications of Hierarchical N-body Techniques for Multiprocessor Architecture

box 4, folder 58

Implications of Hierarchical N-body Techniques for Multiprocessor Architecture 1992 Jan

box 4, folder 59

Implications of Non-Binary Sized Instructions 1992 May 19-21

box 4, folder 60

Improved Models for Switch-level simulation Author: Chorng-Yeong Chu

box 4, folder 61

Improving Locality and Parallelism in Nested Loops 1992 Aug

box 4, folder 62

Incremental Circuit Extraction

box 4, folder 63

Incremental -in-Time Algorithm for Digital Simulation

box 4, folder 64

Efficiency Considerations in Program Synthesis: A Knowledge-Based Approach 1979 Sep

box 4, folder 65

File Access Performance of Diskless Workstations 1984 Jun

box 5, folder 1

Incremental Tools for the Design and Verification of VLSI Circuits 1993

box 5, folder 2

Incremental VLSI Compaction Author: Clyde W. Carpenter 1988 Dec

box 5, folder 3

Instruction Selection by Attributed Parsing 1984 Feb

box 5, folder 4

Integrating Concurrency and Data Abstraction in the COOL Parallel Programming Language

box 5, folder 5

Integrated Pin Electronics for VLSI Functional Testers

box 5, folder 6

Integrating Concurrency and Data Abstraction in a Parallel Programming Language 1992

box 5, folder 7

Integrating Concurrency and Data Abstraction in a Parallel Programming Language 1992 Feb

box 5, folder 8

Integrating Scalar Optimization and Parallelization 1991 Aug

box 5, folder 9

Integration of Message Passing and Shared Memory 1994 Oct

box 5, folder 10

Interleaving: A Multithreading Technique Targetting Multiprocessors and Workstations 1994 Oct 5-7

box 5, folder 11

Interprocedural Analysis Useless for Code Optimization 1987 Nov

box 5, folder 12

Interprocedural Analysis vs. Procedure Integration 1989 Apr

box 5, folder 13

Interprocedural Optimization: Experimental Results 1989

box 5, folder 14

"Interval Methods for Distributed Simulation Systems" Authors: A.R.W. Todesco

box 5, folder 15

"IRSIM: An Incremental MOS Switch-Level Simulator" 1988

box 5, folder 16

John Hennessy A Language for Microcode Description and Simulation in VLSI 1980 July

box 5, folder 17

Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines Rings 1990 Aug

box 5, folder 18

Limits of Control Flow on Parallelism 1992 May 19-21

box 5, folder 19

Limits on Multiple Instruction Issue Authors: M. Smith, M. Johnson, M. Horowitz 1990 July

box 5, folder 20

LISP 1986

box 5, folder 21

LISP 1987 Mar

box 5, folder 22

LISP on a Reduced-Instruction-Set Processor: Characterization and Optimization

box 5, folder 23

Load Balancing and Data Locality in Hierarchical N-Body Methods 1992 Jan

box 5, folder 24

LocusRoute: A Parallel Global Router for Standard Cells 1988

box 5, folder 25

Logic Minimization, Placement Routing in SWAMI

box 5, folder 26

Mable: A Technique for Efficient Machine Stimulation 1994 Oct

box 5, folder 27

Mable: A Technique for Efficient Machine Stimulation 1994 Apr 18-21

box 5, folder 28

MAGIC: the Beta Release UCB-EECS 1985 Aug

box 5, folder 29

Making Effective Use of Shared-Memory Multiprocessors: The Process Control Approach 1991 July

box 5, folder 30

Measurement, Analysis and Improvement of the Cache Behavior of a Shared Data in Cache Coherent Multiprocessors" 1990 Feb

box 5, folder 31

Measurement and Evaluation of the MIPS Architecture and Processor

box 5, folder 32

Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors 1993 Apr

box 5, folder 33

"Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors" 1990 Mar

box 5, folder 34

Memory-Reference Characteristics of Multiprocessor Applicationa under MACH 1988

box 5, folder 35

MemSpy: Analyzing Memory System Bottlenecks in Programs 1992 Jun

box 5, folder 36

"A Methodology for Modeling Inter-processor Traffic in Shared Memory Multiprocessors" 1989 July

box 5, folder 37

MIPS: A Microprocessor Architecture 1982 Oct

box 5, folder 38

MIPS: A VLSI Processor Architecture 1981 Sep

box 5, folder 39

MIPS-X: A 20 MIPS Peak, 32-bit microprocessor with on-chip cache

box 5, folder 40

The MIPS-X External Cache Processor: Functionality and I/O 1987

box 5, folder 41

MIPS-X: The External Interface 1987 Nov

box 5, folder 42

MIPS-X: Instruction Set and Programmer's Manual

box 5, folder 43

The MIPSX Microprocessor Horowitz, Chow 1985

box 5, folder 44

Modeling the Performance of Limited Pointers Directories for Cache Coherence 1991

box 5, folder 45

MTOOL: an Integrated System for Performance Debugging Shared Memory Multiprocessor Applications 1992 May

box 5, folder 46

MTOOL: A Method for Isolating Memory Bottlenecks in Shared Memory Multiprocessor Programs 1991 Aug 12-16

box 5, folder 47

Multi-Level Logic Array Synthesis Author: Rowen, Christopher 1985 July

box 5, folder 48

Multiprocessor Cache Memory Performance: Characterization and Optimization 1992 Aug

box 5, folder 49

Multiprocessor Cache Analysis Using ATUM 1988 Jun

box 5, folder 50

Multiprocessor RISCS: Design Issues R. H. Katz, et al.

box 5, folder 51

MultiTitan-Four Architecture Papers Digital, West. Res. Lab. 1988

box 5, folder 52

Multis: A New Class of Multiprocessor Computers By: Bell

box 5, folder 53

The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range. Author: F. McMahon 1986 Dec

box 5, folder 54

Multiprocessor Performance Debugging and Memory Bottlenecks 1992 Aug

box 5, folder 55

Multiprocessor RISCS: Design Issues Initial Analyses

box 5, folder 56

Multiprocessor Simulation: Achieving Accuracy, Efficiency, and Flexibility 1993 Oct

box 5, folder 57

Multiprocessor Simulation and Tracing Using Tango 1991 Aug 12-16

box 5, folder 58

"Nondeterminism and Unification in Log-Scheme: Integrating Logic and Functional Programming"

box 5, folder 59

On-Chip Instruction Caches for High Performance Processors Anant Agarwal, Paul Chow, Mark Horowitz 1987

box 5, folder 60

Organization and VLSI Implementation of MIPS 1984 Apr

box 6, folder 1

An Overview of the MIPS-X-MP Project #86-300 John Hennessy Mark Horowitz 1986 Apr

box 6, folder 2

Overview and Status of the Stanford DASH Multiprocessor 1991 Apr

box 6, folder 3

Overview of the Stanford U-Code Compiler System

box 6, folder 4

Overview of Work in VLSI Systems and Software Area

box 6, folder 5

A Parallel Adaptive Fast Multipole Method 1993 Nov 15-19

box 6, folder 6

The Parallel Decomposition and Implementation of an Integrated Circuit Global Router 1988 July

box 6, folder 7

"Parallel Distributed-Time Logic Simulation" Authors: L. Soule, A. Gupta

box 6, folder 8

Parallel Global Routing for Standard Cells Author: Rose

box 6, folder 9

Parallel Hierarchical N-Body Methods and Their Implications for Multiprocessors 1993 Mar

box 6, folder 10

Parallelizing Compilers: Implementation and Effectiveness 1993 Jun

box 6, folder 11

Parallel ICCG on a Hierarchical Memory Multiprocessor-- Addressing the Triangular Solve Bottleneck

box 6, folder 12

Parallel Implementation of OPS5 on the Encore Multiprocessor: Results Analysis Authors: Gupta, Tambe, Kalp, Forgy, Newell 1988

box 6, folder 13

Parallel Logic Simulation: an Evaluation of Centralized-Time and Distributed-Time Algorithms 1992 Jun

box 6, folder 14

Parallel Logic Simulation on General Purpose Machines

box 6, folder 15

Parallel OPS5 on the Encore Multimax Authors: Gupta, Forgy, Kalp, Newell, Tambe 1988

box 6, folder 16

"Parallelizing the Simulation of Ocean Eddy Currents" Authors:J. P. Singh J. L. Hennessy 1989 Aug

box 6, folder 17

Partitioning and Scheduling Parallel Programs for Execution on Multiprocessors Author: Vivek Sarkar 1987 Apr

box 6, folder 18

Partitioning parallel Programs for Macro-Dataflow

box 6, folder 19

PASCAL and Pascal* Compiler Systems Author: Hennessy, J. 1979 Aug

box 6, folder 20

Pascal*: A Pascal Based Systems programming language 1980 Jun

box 6, folder 21

The Performance Advantages of Integrating Block Data Transfer in Cache-Coherent Multiprocessors 1994 Oct 5-7

box 6, folder 22

The Performance Advantages of Integrating Message-Passing in Cache-Coherent Multiprocessors 1993 Nov

box 6, folder 23

Performance Debugging Shared Memory Multiprocessor Programs with MTOOL 1991 Nov 18-22

box 6, folder 24

Performance-Directed Memory Hierarchy Design Author: Steven A. Przybylski 1988 Sep

box 6, folder 25

Performance Evaluation of Hybrid Hardware and Software Distributed Shared Memory Protocols 1993 Dec

box 6, folder 26

Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors 1990 Dec

box 6, folder 27

Performance Impact of Data Reuse in Parallel Dense Cholesky Factorization 1992 Jan

box 6, folder 28

The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor 1994 Oct 5-7

box 6, folder 29

David Marple Performance Optimization of Digital VLSI Circuits 1986 Oct

box 6, folder 30

Performance of Update Algorithms for Replicated Data in a Distributed Database 1979 Jun

box 6, folder 31

The Priority-Based Coloring Approach

box 6, folder 32

Procedure Merging with Instruction Caches 1991 Jun 26-28

box 6, folder 33

Process Control and Scheduling Issues for Multiprogrammed Shared-Memory Multiprocessors 1989 Mar 14

box 6, folder 34

Program Analysis and Optimization for Machines with Instruction Cache 1991 Sep

box 6, folder 35

Programming for Different Memory Consistency Models 1992

box 6, folder 36

McFarland

box 6, folder 37

the Programming Language Rascal Author: Paulson, L. 1979 July

box 6, folder 38

Performance Tradeoffs in Cache Design Authors: Przyblysky, Horowitz, Hennessy

box 6, folder 39

Piecewise Linear Models for Rsim 1993 Nov 8-11

box 6, folder 40

Piecewise Linear Models for Switch-Level Simulation 1992 Jun

box 6, folder 41

Precise Delay Generation Using Coupled Oscillators J. Maneatis thesis 1994 Jun

box 6, folder 42

A Portable Machine-Independent Global Optimizer-- Design and Measurements Author: Chow, F. 1983 Dec

box 6, folder 43

Postpass Code Optimization of Pipeline Constraints 1983 July

box 6, folder 44

Precise Delay Generation Using Coupled Oscillators J. M 1993 Dec

box 6, folder 45

A Programming and Problem-Solving Seminar 1985 Jun

box 6, folder 46

Qualifying Examinations in Computer Science 1965-1978 edited by Frank M. Liang 1979 Apr

box 6, folder 47

Rationale, Design and Performance of the Hydra Multiprocessor K. Olukotun, et al. 1994 Nov

box 6, folder 48

REDS: Resistance Extraction for Digital Simulation

box 6, folder 49

Reducing the Cost of Branches McFarling, S. Hennessy, J. 1985

box 6, folder 50

"Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes" 1990 Mar

box 6, folder 51

Reducing Overhead in Counter-Based Execution Profiling 1991 Oct

box 6, folder 52

Research in VLSI Systems Systems Design and Architecture 1981 Mar

box 6, folder 53

Research in VLSI Systems Technical Progress Report 1983-1984

box 7, folder 1

Resumes of Graduate Students 1984 Feb

box 7, folder 2

"Rounding Algorithms for IEEE Multipliers" Authors: M. Santoro, G. Bewick, M. Horowitz

box 7, folder 3

The S-1 Multiprocessor Finnel 1978 Jun

box 7, folder 4

Reverse Synthesis Compilation for Architectural Research 1984 Mar

box 7, folder 5

RISC Architectures P. Chow, J. Hennessy

box 7, folder 6

RISC-Based Processors: Concepts and Prospects Author: John Hennessy 1986 Mar 16-19

box 7, folder 7

Research in VSLI Systems Technical Progress Report 1985 Apr - Oct

box 7, folder 8

Retargetable Compiler Code Generation Author: M. Ganapathi, C. Fischer, J. Hennessy 1982

box 7, folder 9

SAL: A Single Assignment Language for Parallel Algorithms 1983 Sep

box 7, folder 10

Scalable Directories for Cache-Coherent Shared Memory Multiprocessors 1993 Jan

box 7, folder 11

Scalable Directory Schemes for Cache Coherence 1988 Jun

box 7, folder 12

Scalar Privatization: Algorithm and Effect on Compiler Detected 1991 Jan 16

box 7, folder 13

Scaling Parallel Programs for Multiprocessors: Methodology and Examples 1992 Aug

box 7, folder 14

A Self-Timed Chip for Division Authors: Williams, Horowitz, et al

box 7, folder 15

Self-Timed Logic Using Current-Sensing Completion Detection (CSCD) 1991 Oct 14-16

box 7, folder 16

A Self-Timed SRT Diversion Chip Authors: Williams, T., Horowitz, M., et al. 1986 Oct 1

box 7, folder 17

Semantic Foundations of Jade 1992 Jan

box 7, folder 18

"Semantic Predicates in Parser Generators" Author: M. Ganapathi 1989

box 7, folder 19

Shared Memory vs. Message Passing Architectures: An Application Based Study Authors: Martonosi, Gupta

box 7, folder 20

A Short Guide to MIPS Assembly Instructions Authors: Gross, T. Gill, J. 1983 Nov

box 7, folder 21

Signal Delay in RC Tree Netowkrs Horowitz, M. 1983

box 7, folder 22

A Simple and Efficient Implementation Approach for Single Assignment Language (Technical Summary) 1988 July

box 7, folder 23

A Simple Interprocedural Register Allocation Algorithm and its Effectiveness for LISP

box 7, folder 24

A Single Chip LSI High-Speed Functional Tester Authors: J. Miyamoto M.A. Horowitz 1987 Apr 1

box 7, folder 25

SLIM: A Simulation Implementation Language for VLSI Microcode

box 7, folder 26

Soft Configurable Water Scale integration: Design, Implementation, and Yield Analysis. Author: M. Blatt 1990 Jun

box 7, folder 27

Specifying System Requirements for Memory Consistency Models 1993 Dec

box 7, folder 28

Spectral Lower-Bound Techniques… Brandman 1987 Mar

box 7, folder 29

A Spectral Lower-Bound Technique for the Size of Decision Trees and Two-Level Circuits

box 7, folder 30

"SPIM: A Pipelined 64 x 64 bit Iterative Multiplier" Authors: M. Santoro, M.A. Horowitz 1989 Apr

box 7, folder 31

SPLASH: Stanford Parallel Applications for Shared-Memory 1991 Apr

box 7, folder 32

SPLASH: Stanford Parallel Applications for Shared-Memory 1992 Jun

box 7, folder 33

SPUR: A VLSI Multiprocessor Workstation M. Hill et al 1985 Nov 8

box 7, folder 34

SRT Division Diagrams and Their Usage… Williams/Horowitz 1986 Nov

box 7, folder 35

Sail 1976 Aug

box 7, folder 36

Monitor Command Manual 1976 Jan

box 7, folder 37

Booklet of Viewgraphs Stanford Computer Forum 1981 Feb

box 7, folder 38

Stanford U-Code

box 7, folder 39

A Static Ram as a Fault Model Evaluator John Acken Mark Horowitz

box 7, folder 40

Streams in a Single-Assignment Language

box 7, folder 41

STRIP: A Self-Timed RISC Processor 1992 July

box 7, folder 42

Study of Compiler Detection of Loop-Level Parallelism Technical Summary (A) 1992 Oct 8

box 7, folder 43

The Stanford DASH Multiprocessor 1992 Mar

box 7, folder 44

Suficient System Requirements for Supporting the PLPC Memory Model 1993 Dec

box 7, folder 45

Suitability of Message Passing Computers for Implementing Production Systems

box 7, folder 46

Summary of MIPS Instructions 1983 Nov

box 7, folder 47

"Super-Scalar Processor Design" Author: William M. Johnson (thesis) 1989 Jun

box 7, folder 48

Support for Speculative Execution in High-Performance Processors 1992 Nov

box 7, folder 49

Computer Science Department 1987 Oct

box 7, folder 50

Tau Epsilon Chi A System for technical Text 1978 Sep

box 7, folder 51

Tau Epsilon Chi A System for technical Text 1978 Nov

box 7, folder 52

Tau Beta Pi Teaching Survey 1976-1977